1. Field of the Invention
The present invention relates to a data processing apparatus and, more particularly, to a data processing apparatus suitable for attaining high-speed processing of print data in a recording apparatus, which receives image data transferred from a host computer and prints the received image data.
2. Related Background Art
In recent years, as the resolutions and speeds of recording apparatuses increase, the volume of print data transferred from a host computer is becoming very large. In a method of processing such large volume of print data, high-speed processing is realized by increasing the speed and the number of bits (e.g., from 8 bits to 16 bits or to 32 bits) of CPUs, or by exploiting data processing using hardware based on DMA (direct memory access) processing.
For example, in the prior art (prior art 1) shown in FIG. 5, when a DMA processor starts processing, it interrupts the operation of a CPU by requesting the use of a bus of it, and executes DMA upon gaining access to the bus. In this case, the operation of the CPU and DMA processing are alternately executed, and an improvement in total processing speed is limited.
On the other hand, in a system that executes DMA processing while a CPU is accessing a program ROM as in the prior art (prior art 2) shown in FIG. 6, if the CPU is executing a command such as multiplications and divisions that require a long processing time, the processing interval of DMA is prolonged.
More specifically, control for allocating the DMA processing time for realizing high-speed processing by hardware, and the software execution time of the CPU, poses a problem.
Various recording apparatuses such as a printer, copying machine, facsimile apparatus, wordprocessor, and the like use CPUs (Central Processing Units). The CPU operates in accordance with a program that describes the processing contents.
FIG. 8 is a block diagram showing a conventional recording apparatus.
A CPU 101 has a WAIT function, and an ASIC (Application Specific IC) 103 and a ROM (Read Only Memory) 104 are connected to the CPU 101 via a system bus 102. The ROM 104 stores a control program for managing the entire recording apparatus, font information, and the like. A RAM (Random Access Memory) 106 is connected to the ASIC 103 via a RAM bus 105. The RAM 106 is used as, e.g., a print control work area for writing and reading information. The ASIC 103 is used for driving the ROM 104 and the RAM 106, and performing print control, and the like.
Furthermore, the CPU 101 and the ASIC 103 exchange a bus control signal 107. The ASIC 103 and the ROM 104 exchange a ROM control signal 108. The ASIC 103 and the RAM 106 exchange a RAM control signal 109.
FIG. 9 is a timing chart when the CPU 101 accesses the ROM 104 in the arrangement shown in FIG. 8. The CPU 101 generates an address, a signal indicating the type of memory access (i.e., a signal indicating a read/write signal), and the like. Subsequently, the CPU 101 asserts a signal indicating that the address, the type of memory access, and the like are determined (to be referred to as a "signal ASX" hereinafter) (timing t.sub.31), sets the data direction to be the input, and asserts a signal DSX. The CPU 101 then determines the bus cycle time based on a signal WAIT (to be described later), and negates the signal DSX after an elapse of a predetermined period of time. At the same time, the CPU 101 receives data and negates the signal ASX (timing t.sub.33), thus preparing for the next access.
Upon reception of the signal ASX from the CPU 101, the ASIC 103 determines the memory device to be accessed based on the address at that time, determines the type of memory access based on the signal indicating the type of memory access, and supplies a predetermined memory control signal to a predetermined memory device. At this time, when the selected device has a low access speed, the ASIC 103 asserts a signal WAIT for requesting to postpone the memory access, and negates the signal WAIT at the timing at which the selected memory device can respond to the memory access. Upon reception of the control signal from the ASIC 103, the selected memory device reads out data from an appropriate address (timing t.sub.32).
FIG. 10 is a timing chart when the CPU 101 accesses the RAM 106. In this case, the RAM 106 comprises a D-RAM, and its access speed is faster than the bus cycle. Hence, in the following description, the RAM 106 will be referred to as a D-RAM.
In this case, the CPU 101 generates the address of the D-RAM and a signal indicating a read, and thereafter, asserts a signal ASX. Furthermore, the CPU 101 sets the data direction to be the input, and asserts a signal DSX. Upon reception of the signal ASX from the CPU 101, the ASIC 103 determines the D-RAM to be accessed on the basis of the address at that time, sets a ROW address at the address of the D-RAM (timing t.sub.41), and asserts a signal RASX. After an elapse of a pre-set period of time, the ASIC 103 sets a COLUMN address at the address of the D-RAM (timing t.sub.42), and asserts a signal CASX (timing t.sub.43). At the same time, the ASIC 103 asserts a signal OEX as a command for requesting the D-RAM to output data.
Upon reception of the control signal 109 from the ASIC 103, the D-RAM outputs the contents at the designated address onto the RAM bus 105 (timing t.sub.44). At this time, since the access speed of the D-RAM is faster than the bus cycle, as described above, the ASIC 103 negates the individual control signals at predetermined timings while negating the signal WAIT, thus returning the data on the RAM bus 105 to the system bus 102. When the CPU 101 confirms at the WAIT signal sampling timing that the signal WAIT is negated, it negates the signals ASX and DSX (timing t.sub.45), and at the same time, latches the data, thus ending the bus cycle.
FIG. 11 is a timing chart for explaining the outline of the DMA (direct memory access) of the ASIC 103. The DMA is processing in which the ASIC 103 directly accesses the D-RAM using the released RAM bus 105 in a bus cycle (e.g., at the time of ROM access or the like) in which the CPU 101 uses only the system bus 102.
The CPU 101 generates an address and a signal indicating the type of memory access (read or write access, or the like), and asserts a signal indicating that the address, the type of memory access, and the like are determined (e.g., a signal ASX). The CPU 101 then sets the data direction to be the input, and asserts a signal DSX (timing t.sub.51). The CPU 101 determines the bus cycle time on the basis of a signal WAIT, and negates the signal DSX after an elapse of a predetermined period of time (timing t.sub.55). At the same time, the CPU 101 receives data, and negates the signal ASX to prepare for the next access. Upon reception of the signal ASX from the CPU 101, the ASIC 103 determines the memory device to be accessed based on the address at that time, determines the type of memory access based on the signal indicating the type of memory access, and supplies a predetermined control signal to a predetermined memory device.
At this time, when the selected device has a low access speed, the ASIC 103 asserts a signal WAIT for requesting to postpone the memory access, and negates the signal WAIT at the timing at which the selected memory device can respond to the memory access. Upon reception of the control signal from the ASIC 103, the selected memory device reads out data from an appropriate address. If a DMA request is generated inside the ASIC 103, the ASIC 103 generates the next RAM access using the RAM bus 105 released simultaneously with the above-mentioned operation (at this time, assume that the access speed of the D-RAM is faster than the bus cycle).
The ASIC determines the D-RAM to be accessed on the basis of the address the DMA to which is requested, sets a ROW address of the DMA of the D-RAM (timing t.sub.50), and asserts a signal RASX (timing t.sub.51). Thereafter, after an elapse of a pre-set period of time, the ASIC 103 sets a COLUMN address of the DMA at the address of the D-RAM (timing t.sub.52), and asserts a signal CASX (timing t.sub.53). In this case, the ASIC 103 asserts a signal OEX that requests the D-RAM to output data simultaneously with asserting the signal CASX (timing t.sub.53). Upon reception of the control signal 109 from the ASIC 103, the D-RAM outputs the contents at the designated address onto the RAM bus 105. The ASIC 103 latches the data on the RAM bus 105 at that time (timing t.sub.54), and transfers the latched data to the internal block that generated the DMA request.
However, in the above-mentioned prior art, when the CPU 101 issues a loop command (a continuous RAM access command such as a block transfer command or the like without any command fetch) while the DMA request is generated, the ASIC 103 postpones the DMA until the loop command ends, and executes the DMA when the RAM bus 105 is released.
However, since the recording apparatus involves many DMA processing operations with limited processing times like recording head control DMA processing, and the like, the DMA cannot be postponed for a long period of time.
In the prior art, in order to avoid the above-mentioned problem, the loop command is inhibited from being used, or the RAM bus 105 is forcibly released by executing bus intervention or arbitration. However, when the method of inhibiting the use of the loop command is used, the loop command with a great merit such as a block transfer command or the like that allows high-speed transfer of data cannot be used, thus posing another problem. If bus intervention is used, a complex bus intervention circuit is required, and DMA efficiency is impaired due to the presence of the negotiation time for bus intervention.
The present invention has been made in consideration of the above-mentioned problems, and has as its object to provide a recording apparatus which allows an ASIC to execute DMA even when a RAM bus is not released.